During the manufacture of semiconductor devices such as dynamic random access memories (DRAMs), microprocessors, and logic devices, several conductive structures are commonly formed. For example, transistor gates and capacitor bottom (storage) and top plates, typically manufactured from doped polysilicon, and interconnects and runners, typically formed from aluminum and/or copper, are formed on various types of devices.
A design goal of semiconductor engineers is to decrease feature sizes while maintaining adequate conductivity of interconnects and sufficient capacitance within storage capacitors. With increasing device density, polysilicon becomes less desirable as a material to form conductive structures such as storage capacitors and other conductive features. A conductive material which has been used for various semiconductor device structures such as capacitor plates in ferroelectrics devices is ruthenium oxide (RuO2). Ruthenium oxide exhibits good step coverage and a uniform thickness across various topographies. However, RuO2 is not stable and disproportionates into a strong oxidizer. It will, over time, oxidize various metal layers which are in close proximity. For example, if RuO2 is used as a capacitor bottom plate, it will oxidize a titanium nitride or tungsten nitride top plate through a tantalum pentoxide (Ta2O5) capacitor dielectric. Further, a barrier layer must be formed to protect a polysilicon contact pad from the RuO2, as the RuO2 will oxidize the polysilicon and result in a bottom plate being electrically isolated from the contact pad by a silicon dioxide layer.
Attempts have also been made to use ruthenium metal as capacitor plates or as various other structures, as ruthenium metal is stable and is easily planarized during chemical mechanical polishing (CMP). However, previous methods for forming a ruthenium metal layer, for example using chemical vapor deposition (CVD), result in a layer which has poor adhesion to an underlying silicon dioxide layer.
Various layers have been proposed to enhance the adhesion of a metal layer to a dielectric. The following US patents, each having at least one inventor in common with the present application and assigned to Micron Technology, Inc., are each incorporated herein as if set forth in its entirety. Each patent describes the use of adhesion layers: U.S. Pat. Nos. 5,990,559; 6,197,628; 6,204,172, 6,218,297; 6,281,161; 6,284,655; 6,323,511; 6,403,414; 6,421,223; 6,461,909; 6,462,367; 6,495,458. In particular, U.S. Pat. No. 6,462,367 discloses in one embodiment an adhesion layer for adhering ruthenium to a dielectric, the adhesion layer comprising RuSixOy, where “x” and “y” are in the range of about 0.01 to about 10, with a thickness of between about 10 angstroms (Å) to about 1,000 Å.
While an adhesion layer is often desired or required to ensure a device does not malfunction as a result of a layer (such as ruthenium metal) peeling from an underlying layer (such as a silicon dioxide dielectric), the functionality of some completed structures is enhanced if the distance between two layers is minimized. Thus, the inclusion of an extra layer, the adhesion layer, between two such layers can be detrimental. Further, adding additional layers to a complicated process can introduce additional variation which may result in decreased device performance or predictability of device functionality.
A method for forming a ruthenium metal layer on a dielectric layer which reduces or eliminates the problems described above, and the structure resulting from the method, would be desirable.